1. Field of the Invention
This invention relates to the field of semiconductor integrated circuits, and particularly to an improvement in reducing substrate noise coupling in mixed signal circuits or circuits containing both analog and digital circuits on a common silicon substrate.
2. Description of the Related Art
So called mixed signal integrated circuits have been gaining in market share of the integrated circuit market. Typically, these integrated circuits contain both analog and digital circuits. With the low cost and high speed processing capabilities of Digital Signal Processors (DSPs) many analog applications now use on board DSPs to perform signal processing rather than analog means as was done for earlier applications. Also, the input signal of many analog applications is formatted digitally or, conversely, the output is formatted digitally. Thus, if low cost single chip solutions are to be used, both digital and analog circuits must coexist on the same substrate. A single chip containing both digital and analog circuits is often referred to as mixed signal MOS integrated circuit.
Because of the noise associated with the transient switching behavior of digital circuits, it is desirable to minimize the electrical interaction between the analog and digital circuits of mixed signal chips. This goal is partially met by completely separating the power supply wires or lines associated with each type of circuit. In fact, it is even common to isolate various analog circuit components from each other by using separate power bussing for each of these components. Unfortunately, the substrate remains common to all circuits on the chip and therefore couples noise from one circuit to another. This substrate noise can be amplified by the body to source transconductance of MOS signal transistors and thereby can be injected into analog signal paths.
The primary source of substrate noise injection is the substrate tie which is connected to a noisy ground power supply line. To lower substrate noise it is desirable to have a dedicated bus which connects to all substrate ties but does not connect to Vss or ground power. Unfortunately, most logic cell libraries do not permit the separation of the substrate tie from the Vss power line. Other substrate noise injection sources include transitioning nodes or signal lines which capacitively couple to the substrate. Capacitive noise injecting means include node to substrate capacitances such as N+/P substrate junctions and metal signal lines which are routed over the substrate.
Most commonly, CMOS integrated circuits use a P type substrate which becomes the body of the N channel MOS transistors and therefore, makes the N channel transistors susceptible to substrate noise. The P channel transistors for such cases, however, are relatively immune from substrate noise because of the isolated N well which ties to a positive power supply voltage which can be separate from other positive supply voltages.
FIG. 1 shows a cross section of two N channel transistors, 100A and 100B, connected to different power buses in a standard, epitaxial CMOS process with a P type substrate 101. The epi layer 102 is also P type. Other structures found in this cross section include the poly silicon gate 103A of transistor 100A, the poly silicon gate 103B of transistor 100B, the drain N+ implant 104A of transistor 100A, the drain N+ implant 104B of transistor 100B, the channel doping or implant 105A of transistor 100A, the channel doping or implant 105B of transistor 100B, the source N+ implant 106A of transistor 100A, the source N+ implant 106B of transistor 100B, the P+ substrate tie 107A associated with transistor 100A, the P+ substrate tie 107B associated with transistor 100B, the field oxide region 108, the field implant regions 109, examples of metal interconnect 111 and 112, interlevel dielectric material 113, and interconnect plugs 114 used to connect one level of metal with another.
For the sake of illustration, assume that the N channel transistor 100A is on the digital side and the N channel transistor 100B is on the analog side on a single chip or integrated circuit die. A field oxide gap region 110 is typically used to used to "isolate" the substrate/epitaxial areas of the two different functional regions. In this example it is desired that the analog Vss bus 115B hold the potential of the body region 105B of transistor 100B to a constant, noiseless potential through substrate tie 107B. However, some noise from the digital Vss bus 115A will couple over to the body region 105B via the digital body tie 107A, the epitaxial layer 102, and the heavily doped substrate 101. In examples to be shown later, the ability of substrate tie 107B is very limited in providing noise isolation from the digital Vss bus 115A.
It should be noted that a bulk wafer can also be used in lieu of an epitaxial wafer. In advanced CMOS processes bulk wafers with a heavy substrate doping have been used successfully with generous spacing I/O pad layout rules used to prevent latch-up due to parasitic SCR structures.
One method to significantly reduce such noise is to use to used the so called triple well process. A cross section of two N channel transistors, 100A and 200 are shown in FIG. 2. The N channel transistor 200 has a P type well 204 which is isolated from the epitaxy and the substrate by using an intervening N type layer 201 which is formed using a deep, high energy implant. The isolated P well 204 is connected to Vss 207 via a P+ implant which is the same as that used to form the P+ drain/source implants of the P channel transistor which is not shown. Note that the Vss 207 of transistor 200 is separate from the Vss 115A associated with the left hand N channel transistor 100A. The side walls of the isolated P well 204 are bounded by a vertical implanted N well 203 which extends from the surface of the silicon to the deep N layer 201. To electrically contact the N type regions enclosing the isolated P well 204 there are N+ implant 202 regions at the surface which are formed along with the N channel transistor's drain 104B and source 106B implants. If the N well associated with the P channel transistor is deep enough then this implant can be used as the isolating sidewall implant 203; otherwise a separate implant must be used or a combination thereof. To isolate the body of the N channel transistor 200 from the epitaxial layer 102 and the substrate 101 the enclosing N layers 201 and 203 are connected to an isolated, low noise Vdd via the bus metal 206.
The excellent isolation of N channel transistor 200 from substrate/epitaxy noise voltage comes at a price. At least two implants and implant masking steps must be added to the process: the deep N implant layer 201 and the isolated P well 204. Also, as mentioned earlier, if the N well implant associated with the P channel transistor is not deep enough for use as the sidewall N implant 203 then a third implant and masking layer must also be added to the process. Another problem is that the additional chip area must be used to make frequent deep N layer 201 contacts and frequent isolated P well ties 205. The triple well structure introduces a vertical PNPN device or vertical parasitic SCR which can easily latch up if frequent deep N layer 201 ties and isolated P well ties to the power supply rails are not used. Note also that Vdd busing is required to bias the deep N layer 201 in addition to Vss busing for the isolated P well tie 205. The reduction in layout area efficiency required for the isolating the N channel transistor's body is unacceptable for digital circuits where high substrate noise can be tolerated. For this reason, the "digital" N channel transistor 100A of FIG. 2 is shown with a conventional body connection to the epitaxy 102/substrate 101. Thus, for the analog portion of a mixed signal chip N channel transistors with isolated bodies can be considered if good N channel transistor isolation is required and the chip is not cost sensitive.